1. Field of the Invention
The invention relates to semiconductor package technology and in particular to a wafer-level chip scale package (WLCSP) structure for an optoelectronic device.
2. Description of the Related Art
Digital image devices are widely used in, for example, digital cameras, digital video recorders, cellular phones with image capture function, and monitors. A digital imaging sensor typically includes an optoelectronic device chip, such as a charge-coupled device (CCD) image sensor chip and CMOS image sensor chip.
Such image sensor chips may be packaged by an advanced package technology called “WLCSP”. In the traditional package technology, a wafer having micro-devices, such as electronic devices, electromechanical devices or optoelectronic devices formed thereon, is first diced into multiple chips, and thereafter the chips are packaged. Unlike the traditional package technology, according to WLCSP, micro-devices may be packaged prior to dicing a wafer into multiple chips.
FIGS. 1 and 2 are cross-sections of a pair of package structures for front and back-illuminated optoelectronic devices, respectively. In particular, the optoelectronic devices, such as image sensors, are packaged by WLCSP. In FIG. 1, each package structure comprises a device chip disposed between a pair of glass substrates 100 and 110. The device chip includes a device substrate 106 having micro-devices (not shown) thereon and a dielectric layer 104 formed on the device substrate 106. An extension pad 105 is formed in the dielectric layer 104, comprising a pad portion 103 and an extending portion 101. The device chip is bonded with the glass substrate 100 through a glue layer 102 formed therebetween. Moreover, the device chip is bonded with the glass substrate 110 through a glue layer 108 formed therebetween. A buffer layer 112 is disposed on the glass substrate 110. A metal layer 114 covers the glass substrates 100 and 110 and directly contacts the sidewall of the pad portion 103 of the extension pad 105. A protective layer 116 is disposed on the metal layer 114, having an opening above the buffer layer 112. A solder ball 118 is disposed in the opening to electrically connect the metal layer 114, serving as a connection between internal and external circuits.
In FIG. 2, each package structure also comprises a device chip disposed between a pair of glass substrates 200 and 212. The device chip is reversely placed on a carrier substrate 208, including a device substrate 204 and a dielectric layer 206 between the device and carrier substrates 204 and 208. An extension pad 205 is formed in the dielectric layer 206, comprising a pad portion 203 and an extending portion 201. Glue layers 202 and 210 are employed to bond the device chip to the glass substrates 200 and 212, respectively. Similar to the package structure shown in FIG. 1, a buffer layer 214, a metal layer 216, a protective layer 218 and a solder ball 220 are successively disposed on the glass substrate 212.
In such package structures, the contact area between the package metal layer 114 or 216 and the extension pad 105 or 205 is limited to the thickness of the pad portion 103 or 203 of the extension pad 105 or 205. Accordingly, as the device size is reduced to increase device density, resistance of the extension pad 105 or 205 is increased and device performance reduced. Although the extending portion 101 or 201 of the extension pad 105 or 205 can reduce resistance thereof, the device size may be increased. Thus, difficulty in device size reduction is increased. Moreover, the small contact area between the metal layer and the extension pad is detrimental for adhesion between the metal layer and the extension pad.
Thus, there exists a need for a package structure for an optoelectronic device with increased contact area between the pad and package metal layer.